A semiconductor device with a trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has been proposed. (For example, see patent literature 1.)
Specifically, in the semiconductor device, a P-type base layer is formed in a surface layer portion of an N−-type drift layer. Plural gate trenches are formed to pass through the base layer and reach the drift layer. A gate insulation film and a gate electrode are formed on a wall surface of each gate trench. An N+-type source layer is formed in a surface layer portion of the base layer to abut on a side surface of the gate trench.
A contact trench is formed between adjacent gate trenches to reach the base layer. An N++-type source contact region that has a higher impurity concentration than that of the source layer is formed to abut only on a side surface of the contact trench adjacent to an opening portion of the contact trench. A P+-type base contact region that has a higher impurity concentration than that of the base layer is formed to abut only on a bottom surface of the contact trench.
A source electrode is implanted in the contact trench and connected electrically with the source layer, the source contact region, the base layer and the base contact region. A drain electrode is formed adjacent to a rear surface of the drift layer.